This invention relates to voltage level shifting circuits. More particularly, this invention relates to voltage level shifting circuits with improved switching speed.
Voltage level shifting circuits “shift” signaling voltages from one voltage domain to another. For example, core logic in an integrated circuit may operate at 1.6 volts while signaling between integrated circuit chips may require 3.3 volts. In order to maintain proper circuit communication, voltage level shifting circuits provide an interface between these two voltage domains, shifting 1.6 volt signals to 3.3 volt signals and vice versa.
Voltage level shifting circuits typically receive differential input signals and generate differential output signals (that is, they receive two input signals representing opposite logic states and generate two output signals representing opposite logic states). Each output switches from one logic state (or voltage level) to another logic state (or voltage level) when the input logic states (or voltages levels) switch from one to another. For example, a logical “1” may correspond to a voltage substantially equaling a supply voltage Vdd, while a logical “0” may correspond to a voltage substantially equaling ground. Upon a change in the logic state of an input (e.g., from “0 to 1” or from “1 to 0”), the logic state of an output will change after a finite period of time.
This finite period of time is the transition time required for the circuit output to switch from one logic state to another when the input logic state changes. The amount of voltage shift (e.g., from ground to Vdd) in conjunction with the transition time is the slew rate. In other words, the slew rate is the rate at which the output voltage changes, typically expressed in volts/sec. Preferably, the transition time is as short as possible and the slew rate is as high as possible. Ideally, the transition time is zero and the slew rate is infinite, resulting in an instantaneous output voltage change.
However, because the sizes of sourcing and sinking output drive transistors in known voltage level shifting circuits are often balanced to ensure comparable, if not equal, transition times for both the “0 to 1” and “1 to 0” output transitions, the resulting simultaneous charging and discharging of parasitic and load capacitances during transistor switching often results in a less than satisfactory slew rate. In other words, the sizes of the sourcing and sinking transistors, which affect transistor switching speed, cannot be simultaneously optimal for both the 1 to 0 and 0 to 1 transitions. For example, a small source transistor and a large sink transistor typically have a fast 1 to 0 transition, but a slow 0 to 1 transition. Conversely, a large source transistor and a small sink transistor have a slow 1 to 0 transition, but a fast 0 to 1 transition.
In view of the foregoing, it would be desirable to provide a voltage level shifting circuit with an improved slew rate.